Platform index / Reference design — open console
Stoatworks Labs LOOM
Not a teardown. The open console these teardowns keep pointing at — included because "what would you build instead" is the question every one of them ends on.
The load-bearing finding. 128 inputs, 64 buses, every channel strip computed in FPGA fabric at 96 kHz, speaking Dante, RAVENNA/AES67 and AVB/Milan simultaneously. Where the commercial platforms hide the mixer behind an undocumented register map, here the register map is the deliverable.
Verdict. The contrast that makes the rest of the index legible. Two of the four teardowns concluded that the platform was closed by construction rather than by policy — LOOM is what the alternative costs.
Method
Original design work. Correctness rests on a bit-accurate fixed-point model in Rust, replayed against the RTL in Verilator.
Artifacts examined
- Engineering specification — numbered, verifiable requirements
- Fixed-point model and Verilator testbenches
No manufacturer firmware, binaries or documentation are redistributed here. Artifacts are referenced by name and version only. See themethod and legal statement for the basis on which this analysis was performed and the boundaries it observes.
Hardware architecture
| Item | Finding | Confidence |
|---|---|---|
| Processing platform | AMD Zynq UltraScale+ XCZU7EV (ZCU106 evaluation board) | Public |
| Sample rate | 96 kHz native, 192 kHz selectable | Public |
| Internal format | 32-bit fixed-point Q4.27 with 24 dB headroom, 35-bit Q2.32 coefficients, 59-bit accumulator, TDF2 with full-precision feedback | Public |
| Local I/O | 192 in / 192 out — 16×16 analog, 8×8 AES3, 64×64 MADI, 2 × AES50 | Public |
| Control plane | 4 × Cortex-A53 running Linux, 2 × Cortex-R5F bare-metal DSP supervisor | Public |
Software architecture
| Item | Finding | Confidence |
|---|---|---|
| Routing | Full 192×64 crosspoint, latency-aligned — any input reaches any output in identical total sample count regardless of route depth | Public |
| AoIP | Dante IP Core native on-die, RAVENNA/AES67 + SMPTE ST 2110-30 native in PL, AVB/Milan native in PL — concurrently | Public |
| Core latency target | ≈0.5 ms on the locked native path with SRC bypassed | Public |
What is programmable
- 1All of it
That is the point of including it here.
Open questions
- This is a design, not a shipped product. It is listed here as a reference point, not as a claim of completion.
Status of this entry. Not a teardown — our own open design, included as the contrast case the teardowns keep pointing at. Unless a row says otherwise, nothing on this page has been verified against physical hardware.